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Digital Circuits and Systems Lab.

Digital Circuits and Systems Lab.

Digital Circuits and Systems Lab.

Digital Circuits and Systems Lab.

Digital Circuits and Systems Lab.

Digital Circuits and Systems Lab.

Digital Circuits and Systems Lab.

Digital Circuits and Systems Lab.

Digital Circuits and Systems Lab.

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Digital Circuits and Systems Lab.

Hello, DIGITAL! 

AI Chip.

From chip to system.

Accelerating AI: Designing NPUs for efficient matrix multiplication and efficiently integrating them with CPU.

Hardware.

Neural Processing Unit (NPU)
Processing-in-Memory (PIM)
Datacenter AI
RISC-V CPU based Accelerator Design
Low-power Digital Circuit Design

Software.

AI Model Compression
Quantization
Pruning, Sparsity-aware Computing
Model-specific Compression

We are now looking for enthusiastic and motivated
Integrated MS-PhD Course Students (2028-1).
Please feel free to contact Prof. Ryu if you are interested.

More Details on Contact Page 🡒

Research

We construct an end-to-end system.

Model Training

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Architecture Design

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Circuit Implemention

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Sparse CNN Chip

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NTV Circuit

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Variable-bit NPU

Neural Processing Unit

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Thanos is an energy-efficient keyword spotting processor that leverages hybrid-domain zero-skipping to reduce redundant computations in time, feature, and frequency domains. By skipping low-energy frames, masking irrelevant features, and eliminating insignificant frequency components, Thanos significantly reduces latency (up to 97.2%) and power consumption (up to 99.98%). This approach optimizes both AI and non-AI computations, making it ideal for low-power, always-on voice recognition in edge devices.

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We propose a redundancy-aware DiT (RADiT), a novel software-hardware co-optimization accelerator for DiTs that minimizes redundant operations in the iterative sampling stages. We identify data redundancy by evaluating blockwise input features and skip redundant computations by reusing results from consecutive timesteps. furthermore, to minimize accuracy degradation and maximize computational efficiency, the Dynamic Threshold Scaling Module (DTSM) and Compress and Compare Unit (CCU) are employed in the redundancy detection process. This approach enables DiTs to achieve up to 1.8× and 1.7× faster speeds for image and video 17 generation, respectively, without compromising quality, along 18 with 41% and 45.5% reductions in energy consumption. Our RADiT scheme improves throughput by 1.67× and 1.76× for 20 image and video generation tasks, respectively, while maintaining output quality and significantly reducing energy consumption.

members

Members

Professor

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Please refer to my website for more details

Sungju Ryu

Education

  • 2015~2021: Ph.D. Department of Creative IT Engineering, POSTECH.

  • 2008~2015: B.S. Department of Electrical Engineering, Pusan National University.

Work Experiences

  • 2025.09 ~: Associate Professor, {Department of System Semiconductor Engineering, Department of Electronic Engineering}, Sogang University.

  • 2023.03 ~ 2025.08: Assistant Professor, {Department of System Semiconductor Engineering, Department of Electronic Engineering}, Sogang University.

  • 2021.09 ~ 2023.02: Assistant Professor, {School of Electronic Engineering, Department of Next-Generation Semiconductor}, Soongsil University.

  • 2021.01 ~ 2021.08: Staff Researcher, Samsung Advanced Institute of Technology.

Contact

  • sungju at sogang.ac.kr

Researchers

Seongmin Ki

M.S./Ph.D. Student

Sangkyu Jeon

M.S./Ph.D. Student

Huseok Lee

M.S./Ph.D. Student

Eunsang Son

Incoming

M.S./Ph.D. Student

Gisan Ji

M.S./Ph.D. Student

Taejee Kim

M.S./Ph.D. Student

Sungjae An

M.S./Ph.D. Student

Jiwon Park

Incoming

M.S./Ph.D. Student

Sangyeon Kim

M.S./Ph.D. Student

Jaeha Park

M.S. Student

Hongsik Uhm

M.S./Ph.D. Student

Junyoung Park

Incoming

M.S./Ph.D. Student

Kyuchan Cho

M.S./Ph.D. Student

Jaeung Ryu

M.S. Student

Sunghyun Kim

M.S./Ph.D. Student

Alumni

Hyunmin Kim

M.S. Student

Sanghun Shin

M.S. Student

Gwanghwi Seo

M.S. Student

Youngjun Park

M.S. Student

Jangho Baik

M.S. Student

Yeonggeon Kim

M.S. Student

publications

Publications

2026

Journal [CAL]
Sangkyu Jeon, Jungsul Lee, Eojin Lee*, Sungju Ryu*, "DYCA-HBM: Accelerating Long-Context LLM on HBM-PIM with Dynamic Channel-Allocation," IEEE Computer Architecture Letters (CAL), Accepted for publication. (*: Co-corresponding Authors)
​
Conference [ICCAD]
Jaeung Ryu, Seongmin Ki, Jaeha Park, Sangkyu Jeon, Sungju Ryu, “Mosaic: Fast Sparse Matrix Factorization with Parallel Tiling-Merging Computation,” IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Nov. 2026. (BK21/정보과학회 인정 Computer Science분야 우수국제학술대회)
​
Journal [Nano Convergence]
Sunghyun Kim, Hanbin Cho, Taejee Kim, Huseok Lee, Sungjae An, Sungju Ryu, "Review and Optimization of Image Classification Models for Edge AI Applications," Nano Convergence, Accepted for publication.​
​
Pre-Print [arXiv]
Sanghun Shin*, Sangyeon Kim*, Gisan Ji, Sungju Ryu, “NITRO: High-Performance 3D NAND Flash-Based In-Storage Computing with Enhanced Activation Dataflow,” arXiv:2608.11920, Aug. 2026. (*: Equally contributed authors) (Extended Manuscript of DATE 2026)
​
Conference [DAC]
Yeonggeon Kim, Seongmin Ki, Sangkyu Jeon, Sungju Ryu, “Relay-GS: Reusing Temporal Sort Information for 4D Gaussian Splatting Acceleration,” ACM/IEEE Design Automation Conference (DAC), Jul. 2026. (BK21/정보과학회 인정 Computer Science분야 우수국제학술대회)
​​
Journal [TVLSI]
Gisan Ji*, Sanghun Shin*, Jangho Baik, Wonbo Shim, Sungju Ryu, "E-Flash: Energy-Efficient LLM Mapping on NAND Flash-Based In-Storage Inference Computing," IEEE Transactions on VLSI Systems (TVLSI), Apr. 2026. (*: Equally contributed authors)​
​​​​
Pre-Print [arXiv]
Hyunsung Yoon*, Sungju Ryu*, Jae-Joon Kim, “Sparse-on-Dense: Area and Energy-Efficient Computing of Sparse Neural Networks on Dense Matrix Multiplication Accelerators,” arXiv:2604.26587, Apr. 2026. (*: Equally contributed authors)
​
Pre-Print [arXiv]
Jangho Baik*, Sunghyun Kim*, Gisan Ji, Wonbo Shim, Sungju Ryu, “RecFlash: Fast Recommendation System on In-Storage Computing with Frequency-Based Data Mapping,” arXiv:2604.25338, Apr. 2026. (*: Equally contributed authors)
​
​​​​Conference [DATE]
Sanghun Shin, Gisan Ji, Sungju Ryu, "NITRO: 3D NAND Flash-Based In-Storage LLM Computing with Enhanced Activation Dataflow," Design Automation and Test in Europe (DATE), Apr. 2026. (BK21/정보과학회 인정 Computer Science분야 우수국제학술대회)​
​​​​

2025

Conference [ICCAD]
Sangkyu Jeon, Gisan Ji, Yeonggeon Kim, Youngjun Park, Sangyeon Kim, Sungju Ryu, “OptiRange: An Efficient ReRAM-Based PIM Accelerator with ADC Resolution Optimization,” IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Oct. 2025. (BK21/정보과학회 인정 Computer Science분야 우수국제학술대회)
​
Conference [APCCAS]
Jangho Baik, Gisan Ji, Wonbo Shim, Sungju Ryu, “RecFlash: Fast Recommendation Inference on NAND Flash-Based In-Storage Computing with Embedding-Optimized Data Mapping,” IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Oct. 2025.
​​
Workshop [ESSERC]
Sungju Ryu, “Energy-Efficient Hardware-Software Co-Optimization for Edge AI Devices,” IEEE European Solid-State Electronics Research Conference (ESSERC), Sep. 2025. (Invited)
​
Conference [ISLPED]
Gisan Ji*, Sanghun Shin*, Jangho Baik, Wonbo Shim, Sungju Ryu, “E-Flash: Energy-Efficient DNN Mapping on NAND Flash Memory with State-Switching Algorithm,” IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), Aug. 2025. (Best Paper Candidate) (BK21/정보과학회 인정 Computer Science분야 우수국제학술대회) (*: Equally contributed authors)
​
Journal [JSTS]
Seongmin Ki, Sungju Ryu, "Reducing Communication Overheads in MD Simulations: A Novel Floating-Point Data Compression Approach," Journal of Semiconductor Technology and Science (JSTS), Jun. 2025.
​​
Conference [DAC]
Youngjun Park, Sangyeon Kim, Yeonggeon Kim, Gisan Ji, Sungju Ryu, “RADiT: Redundancy-Aware Diffusion Transformer Acceleration Leveraging Timestep Similarity,” ACM/IEEE Design Automation Conference (DAC), Jun. 2025. (BK21/정보과학회 인정 Computer Science분야 우수국제학술대회)
​​​​
Conference [DATE]
Sangyeon Kim, Hyunmin Kim, Sungju Ryu, "Thanos: Energy-Efficient Keyword Spotting Processor with Hybrid Time-Feature-Frequency-Domain Zero-Skipping," Design Automation and Test in Europe (DATE), Mar. 2025. (BK21/정보과학회 인정 Computer Science분야 우수국제학술대회)​
​​​
Journal [Access]
Gwanghwi Seo, Sungju Ryu, "SpecBoost: Accelerating Tiled Sparse Matrix Multiplication via Dataflow Speculation," IEEE Access, Mar. 2025.

2024

Journal [JSTS]
Sungju Ryu, Jae-Joon Kim, "High-Performance Sparsity-Aware NPU with Reconfigurable Comparator-Multiplier Architecture," Journal of Semiconductor Technology and Science (JSTS), Dec. 2024.
​
Journal [Access]
Thanh-Dat Nguyen, Sungju Ryu*, Ik-Joon Chang*, "TRIO-TCAM: An Area and Energy-Efficient Triple-State-in-Cell Ternary Content-Addressable Memory Architecture," IEEE Access, Dec. 2024. (*: Co-corresponding Authors)
​
Conference [ICCD]
Hyunmin Kim, Sungju Ryu, "NexusCIM: High-Throughput Multi-CIM Array Architecture with C-Mesh NoC and Hub Cores," IEEE International Conference on Computer Design (ICCD), Nov. 2024. (BK21/정보과학회 인정 Computer Science분야 우수국제학술대회)
​
Journal [TCAD]
Sungju Ryu, Jaeyong Jang, Youngtaek Oh, Jae-Joon Kim, "Mobileware: Distributed Architecture with Channel Stationary Dataflow for MobileNet Acceleration," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Sep. 2024.
​​
Conference [ISLPED]
Yeonggeon Kim, Hyunmin Kim, Sungju Ryu, "Statues: Energy-Efficient Video Object Detection on Edge Security Devices with Computational Skipping," ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), Aug. 2024. (BK21/정보과학회 인정 Computer Science분야 우수국제학술대회)
​
Journal [JSTS]
Sungju Ryu, "Resource Analysis on FPGA for Functional Verification of Digital SRAM PIM," Journal of Semiconductor Technology and Science (JSTS), Jun. 2024.

2023 (DIGITAL Lab. Established)

Journal [IEICE ELEX]
Gwanghwi Seo, Sungju Ryu, "Area-Efficient AdderNet Hardware Accelerator with Merged Adder Tree Structure," IEICE Electronics Express, Dec. 2023.
​
Journal [TVLSI]
Sungju Ryu*, Youngtaek Oh*, Jae-Joon Kim, "Binaryware: A High-Performance Digital Hardware Accelerator for Binary Neural Networks," IEEE Transactions on VLSI Systems (TVLSI), Dec. 2023. (*: Equally contributed authors)
​
Conference [ISLPED]
Hyunmin Kim, Sungju Ryu, "Teleport: A High-Performance ShiftNet Hardware Accelerator with Fused Layer Computation," ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), Aug. 2023. (BK21/정보과학회 인정 Computer Science분야 우수국제학술대회)​

2022

Journal [JSTS]
Sungju Ryu, "Review and Analysis of Variable Bit-Precision MAC Microarchitectures for Energy-Efficient AI Computation,"Journal of Semiconductor Technology and Science (JSTS), Oct. 2022.
​
Journal [JSSC]
Sungju Ryu, Hyungjun Kim, Wooseok Yi, Eunhwan Kim, Yulhwa Kim, Taesu Kim, Jae-Joon Kim, "BitBlade: Energy-Efficient Variable Bit-Precision Hardware Accelerator for Quantized Neural Networks," IEEE Journal of Solid-State Circuits (JSSC), Jun. 2022.​​

2021

Conference ​​​[ICCAD]
Sungju Ryu, Youngtaek Oh, Jae-Joon Kim, "Mobileware: A High-Performance MobileNet Accelerator with Channel Stationary Dataflow," IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Nov. 2021. (BK21/정보과학회 인정 Computer Science분야 우수국제학술대회)
 
Journal [JSSC]
Sungju Ryu, Jongeun Koo, Wook Kim, Yonghwan Kim, Jae-Joon Kim, "Variation-Tolerant Elastic Clock Scheme for Low-Voltage Operations," IEEE Journal of Solid-State Circuits (JSSC), Jul. 2021.
​
Journal [TODAES]
Naebeom Park, Sungju Ryu, Jaeha Kung, Jae-Joon Kim, "High-Throughput Near-Memory Processing on CNNs with 3D HBM-like Memory," ACM Transactions on Design Automation of Electronic Systems, Jun. 2021.
​​
Conference [DATE]
Sungju Ryu, Youngtaek Oh, Taesu Kim, Daehyun Ahn, Jae-Joon Kim, "SPRITE: Sparsity-Aware Neural Processing Unit with Constant Probability of Index-Matching," Design Automation and Test in Europe (DATE), Feb. 2021. (BK21/정보과학회 인정 Computer Science분야 우수국제학술대회)​​

Before 2021

Conference [DAC]
Hyungjun Kim, Yulhwa Kim, Sungju Ryu, Jae-Joon Kim, "Algorithm-Hardware Co-Design for In-Memory Neural Network Computing with Minimal Peripheral Circuit Overhead," ACM/IEEE Design Automation Conference (DAC), Jul. 2020. (BK21/정보과학회 인정 Computer Science분야 우수국제학술대회)
​
Journal [JSTS]
Jongeun Koo, Jinseok Kim, Sungju Ryu, Chulsoo Kim, Jae-Joon Kim, “Area-Efficient Transposable Crossbar Synapse Memory Using 6T SRAM Bit Cell for Fast Online Learning of Neuromorphic Processors,” Journal of Semiconductor Technology and Science (JSTS), Apr. 2020.
​​​
Conference [CICC]
Sungju Ryu, Hyungjun Kim, Wooseok Yi, Jongeun Koo, Eunhwan Kim, Yulhwa Kim, Taesu Kim, Jae-Joon Kim, "A 44.1TOPS/W Precision-Scalable Accelerator for Quantized Neural Networks in 28nm CMOS," IEEE Custom Integrated Circuits Conference (CICC), Mar. 2020.
​
Conference [A-SSCC]
Jongeun Koo, Eunhwan Kim, Seunghyun Yoo, Taesu Kim, Sungju Ryu, Jae-Joon Kim, “Configurable BCAM/TCAM Based on 6T SRAM Bit Cell and Enhanced Match Line Clamping,” IEEE Asian Solid-State Circuits Conference (A-SSCC), Nov. 2019.
​
Conference [DAC]
Sungju Ryu, Hyungjun Kim, Wooseok Yi, Jae-Joon Kim, "BitBlade: Area and Energy-Efficient Precision-Scalable Neural Network Accelerator with Bitwise Summation," ACM/IEEE Design Automation Conference (DAC), Jun. 2019. (BK21/정보과학회 인정 Computer Science분야 우수국제학술대회)
​
Journal [IEICE ELEX]
Jongeun Koo, Eunhyeok Park, Dongyoung Kim, Junki Park, Sungju Ryu, Sungjoo Yoo, Jae-Joon Kim, "Low-Overhead, One-Cycle Timing-Error Detection and Correction Technique for Flip-Flop Based Pipelines," IEICE Electronics Express, May. 2019.
​
Conference [CICC]
Jongeun Koo, Jinseok Kim, Sungju Ryu, Chulsoo Kim, Jae-Joon Kim, “Area-Efficient Transposable 6T SRAM for Fast Online Learning in Neuromorphic Processors,” IEEE Custom Integrated Circuits Conference (CICC), Apr. 2019.
​
Journal [TVLSI]
Sungju Ryu, Naebeom Park, Jae-Joon Kim, "Feedforward-Cutset-Free Pipelined Multiply-Accumulate Unit for the Machine Learning Accelerator," IEEE Transactions on VLSI Systems (TVLSI), Vol. 27, No. 1, pp 138-146, Jan. 2019.
​
Conference [ISLPED]
Sungju Ryu, Jongeun Koo, Jae-Joon Kim, "Low Design Overhead Timing Error Correction Scheme for Elastic Clock Methodology," IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), Jul. 2017. (BK21/정보과학회 인정 Computer Science분야 우수국제학술대회)
​​
Conference [A-SSCC]
Jongeun Koo, Eunwoo Song, Eunhyeok Park, Dongyoung Kim, Junki Park, Sungju Ryu, Sungjoo Yoo, Jae-Joon Kim, “Area-Efficient One-Cycle Correction Scheme for Timing Errors in Flip-Flop Based Pipelines,” IEEE Asian Solid-State Circuits Conference (A-SSCC), Nov. 2016.
Chips

Chips

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1. Chip K (Kimdaegeon)

  • DB-out: July 24, 2023.

  • Technology: Samsung 28nm CMOS

  • Designed By: Seongmin Ki, Gwanghwi Seo

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3. Chip R (Ricci)

  • DB-out: November 25, 2024.

  • Technology: Samsung 28nm CMOS

  • Designed By: Seongmin Ki, Sangyeon Kim

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2. Chip T (Teilhard)

  • DB-out: July 22, 2024.

  • Technology: Samsung 28nm CMOS

  • Designed By: Seongmin Ki, Yeonggeon Kim

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4. TBD

  • DB-out: ???

  • Technology: Samsung 28nm CMOS

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